1. Field of the Invention
The present disclosure generally relates to methods of forming a semiconductor circuit element and to a semiconductor circuit element, and, more particularly, to forming a semiconductor circuit element having two semiconductor devices, one of which comprises a ferroelectric high-k material and the other comprising a high-k material different from the ferroelectric high-k material.
2. Description of the Related Art
In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. Particularly, the demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes ranging even into the deep sub-micron regime; the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 10 nm. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs can be made much smaller than discreet circuits composed of independent circuit components. The majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or simply MOS transistors), and passive elements, such as resistors and capacitors, integrated on a semiconductor substrate with a given surface area. Typically, present-day integrated circuits involve millions of single circuit elements formed on a semiconductor substrate.
The basic function of a FET or a MOSFET is that of an electronic switching element, wherein a current through a channel region between two contact regions, referred to as source and drain, is controlled by a gate electrode, which is disposed over the channel region and to which a voltage relative to source and drain is applied. Particularly, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of a MOSFET is changed and the characteristic voltage level, usually called “threshold voltage” and in the following referred to as Vt, characterizes the switching behavior of a MOSFET. In general, Vt depends nontrivially on the transistor's properties, e.g., materials, dimensions, etc., such that the implementation of a desired Vt involves plural steps of adjustment and fine-tuning during the fabrication process.
Currently, the most common digital integrated circuits built today use CMOS logic, which is fast and offers a high circuit density and low power per gate. CMOS devices or “complementary symmetry metal oxide semiconductor” devices, as sometimes referred to, make use of complementary and symmetrical pairs of P-type and N-type MOSFETs for implementing logic functions. Two important characteristics of CMOS devices are the high noise immunity and low static power consumption of a CMOS device because the series combination of complementary MOSFETs in a CMOS device draws significant power only momentarily during switching between on- and off-states, since one transistor of a CMOS device is always in the off-state. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example, transistor-transistor logic (TTL) or NMOS logic, which normally have some standing current even when not changing state. In current CMOS technologies, standard transistors and IO devices have the same high-k dielectric and metal electrode, whereas, in comparison with standard devices, the SiO2 oxide of IO devices is thicker.
In efforts to improve memory arrays, ferroelectric gate field effect transistors (FeFETs) have been recently in the focus of research. In general, ferroelectric materials have dielectric crystals which show a spontaneous electric polarization similar to ferromagnetic materials showing a spontaneous magnetization. Upon applying an appropriate external electric field to a ferroelectric material, the direction of polarization can be reoriented. The basic idea is to use the direction of spontaneous polarization in ferroelectric memories for storing digital bits. In FeFETs, the effect that one makes use of is the possibility to adjust the polarization state of a ferroelectric material on the basis of appropriate electrical fields which are applied to the ferroelectric material which, in a FeFET, is usually the gate oxide. Since the polarization state of a ferroelectric material is preserved unless it is exposed to a high, with regard to the polarization state, counter-oriented electrical field or a high temperature, it is possible to “program” a capacitor formed of ferroelectric material such that an induced polarization state reflects an information unit. Therefore, an induced polarization state is preserved, even upon removing an accordingly “programmed” device from a power supply. In this way, FeFETs allow the implementation of non-volatile electrically-switchable data storage devices.
On the basis of ferroelectric materials, it is possible to provide non-volatile memory devices, particularly random-access memory devices similar in construction to DRAM devices, but differing in using a ferroelectric layer instead of a dielectric layer such that non-volatility is achieved. For example, the 1T-1C storage cell design in a FeRAM is similar in construction to the storage cell in widely used DRAM in that both cell types include one capacitor and one access transistor—a linear dielectric is used in a DRAM cell capacitor, whereas, in a FeRAM cell capacitor, the dielectric structure includes a ferroelectric material. Other types of FeRAMs are realized as 1T storage cells which consist of a single FeFET employing a ferroelectric dielectric instead of the gate dielectric of common MOSFETs. The current-voltage characteristic between source and drain of a FeFET depends in general on the electric polarization of the ferroelectric dielectric, i.e., the FeFET is in the on- or off-state, depending on the orientation of the electric polarization state of the ferroelectric dielectric. Writing of a FeFET is achieved in applying a writing voltage to the gate relative to source, while a 1T-FeRAM is read out by measuring the current upon applying a voltage to source and drain. It is noted that reading out of a 1T-FeRAM is non-destructive.
Though a FeFET or a ferroelectric capacitor represent in theory very promising concepts for complex semiconductor devices, it is a difficult task to identify appropriate ferroelectric materials which are compatible with existing advanced manufacturing processes of complex devices, particularly at very small scales. For example, commonly-known ferroelectric materials, such as PZT or perovskites, are not compatible with standard CMOS processes. According to present understanding, hafnium (Hf) materials which are used in current fabrication technologies exhibit a paraelectric behavior due to the predominantly monoclinic crystal structure present in HfO2. However, recent research results indicate that dielectric materials on the basis of hafnium oxide may represent promising candidates for materials with ferroelectric behavior to be used in the fabrication of ferroelectric semiconductor devices of ICs. For example, it was shown that the monoclinic structure may be suppressed in Zr, Si, Y and Al-doped hafnium oxide materials and stabilized crystal structures of ferroelectric nature were obtained in experiments with accordingly-doped samples.
In conventional HK/MG (high-k/metal gate) FEOL (front end of line) process flows, the thick high-k material of FeFET devices is formed in parallel to the high-k gate oxide of logic devices. Herein, a stack is formed in conventional integration approaches over high-k materials in the gate structure of FeFET devices, the stack comprising ferroelectric high-k material and the logic high-k material. Although this stack of ferroelectric high-k material and logic high-k material shows ferroelectric properties, the speed and function of the FeFET devices is negatively affected by parasitic capacitances appearing in the stack. This problem is present in FeFET integration, independent of whether a gate last or replacement gate technique or a gate first technique is employed.
Gate last or replacement gate techniques suffer the problem that the critical dimension of gate structures of FeFET devices is limited by the thick high-k layer of FeFET devices. The reason is that, with gate trenches being filled after gate patterning in replacement gate techniques, the additional ferroelectric layer structures to be formed in the gate trenches reduce the space in the gate trench which is left to the replacement gate materials. For example, in comparing gate structures of gate last and gate first techniques, the initial critical dimension of gate structures in gate last or replacement gate techniques has to be increased by at least 20 nm in comparison to gate first approaches in order to accommodate for the work function adjusting material layer(s) and the gate electrode material.
Furthermore, in gate last or replacement gate approaches close to the 28 nm technology node employing early nickel silicide, an activation anneal for ferroelectric high-k material is limited to temperatures at 450° C. or less. Alternative approaches using replacement gate schemes with late nickel silicidation considerably increase the complexity of conventional gate last or replacement gate process flows.
In view of the above-described situation, it is, therefore, desirable to integrate a full functional FeFET device into existing process flows in gate first and gate last approaches without increasing the complexity of existing process flows and addressing, at least partially, the aforementioned issues.